Workshop on VLSI Circuit Design
Get hands-on experience in the world of VLSI with our workshop on “VLSI Circuit Design.” Designed for BTech students and aspiring MTech innovators, this session will introduce participants to transistor-level CMOS digital logic-gate design using the SPICE tool and PTM MOSFET models, along with simulation and analysis. Students will explore input pattern-dependent delays, estimate the power using measure commands, and understand transistor sizing for driving capacitive loads. The workshop will conclude with a demonstration of inverter design based on Cadence EDA tools. Explore the fundamentals of VLSI design and take your first step into the future of Semiconductor-based IC Design.
Speakers
Senior Lecturer
School of Engineering and Applied Science
MS (The University of Texas at Arlington, USA)
Research Interests: VLSI Technology And Design, Embedded System Design, Internet Of Things, Human Computer Interaction
Associate Professor
School of Engineering and Applied Science
PhD (Portland State University)
Research Interests: Applications of Computer Engineering in Indian Road Safety Audit, Drone based data collection for Indian Roads; Digital VLSI Architectures - Verilog HDL based Implementation of Arithmetic-Logic Sub-systems, Neuromorphic (Neural Networks) sub-systems, and CV/ML algorithms
Date: Wednesday, June 17, 2026
Time: 9:00 AM - 1:00 PM
Venue: GICT Building, Central Campus
