In December 2020, Mazad S. Zaveri re-joined the School of Engineering and Applied Science (SEAS), at Ahmedabad University (AU), as associate professor.

He worked as associate professor at Pandit Deendayal Petroleum University, Gandhinagar during Decemeber 2018 to November 2020.  He was also the incharge Head of the ICT Department, at PDPU during July-August 2020. 

He worked as assistant professor at Ahmedabad University during December 2014 to November 2018. He also worked as assistant professor, at the Dhirubhai Ambani Institute of Information and Communication Technology (DAIICT), Gandhinagar, during June 2010 to November 2014. During January to May 2014, he was also a visiting faculty at the Indian Institute of Information Technology, Vadodara.

During 2003-2009, he worked as research assistant at the (erstwhile "Oregon Graduate Institute") Oregon Health and Science University, and Portland State University, under research funding from NSF and DARPA. 

Mazad S. Zaveri got his PhD in Electrical and Computer Engineering from Portland State University in 2009, his MSE in Electrical Engineering (specialization: Digital CMOS VLSI) from Arizona State University in 2003, and his BE in Instrumentaton and Control Engineering from Gujarat University in 2000. He passed his HSC and SSC (school certification exams) from St. Xavier's School - Loyola Hall, Ahmedabad.

Mazad S. Zaveri's research interests are in the areas of: digital neuro-morphic VLSI architectures, arithmetic-logic Low-PDP digital CMOS circuits and sub-systems. He has guided several MTech and BTech Theses/Projects, mostly related to the area: digital neuro-morphic VLSI systems.

He has guided two PhD candidates: (1) Dr. Manan Mewada, in the area: digital CMOS low-PDP adder circuits; (2) Dr. Ankur Changela, in the area: FPGA implementation of high-radix and mixed-radix CORDIC

Mazad S. Zaveri has taught courses in the digital VLSI/Electronics area, such as: Digital CMOS VLSI Design, VLSI Sub-system Design, Computer Organization, Embedded Systems using ATMEGA microcontrollers, Digital Logic Design and Verilog HDL, Basic Electronic Circuits.

Mazad S. Zaveri is a Parsi-Zoroastrian, whose native place is Devgadh Baria (in Panchmahal/Dahod district of Gujarat).

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https://publons.com/researcher/AAD-9475-2019/

Web of Science ID: AAD-9475-2019

https://www.scopus.com/authid/detail.uri?authorId=25822883700

Scopus Author ID: 25822883700

https://orcid.org/0000-0002-3840-8373

ORCID ID: 0000-0002-3840-8373

• Research Areas:

  • Digital CMOS VLSI Circuits and Architectures 
    • Low power-delay product arithmetic/logic CMOS circuits (or VLSI sub-systems)
  • Verilog HDL / FPGA based implementations for arithmetic/logic subsystems
  • Applications of Computer Engineering in Indian Road Safety Audit;
    • Drone based image/video datasets/collection for Indian Roads; Annotation and Labelling of datasets, for use in ML and Computer Vision applications  for Road Safety Audit
    • Link to our video: https://www.youtube.com/watch?v=3NYZnBAcPuY

• PhD students:

  • Completed:
    • Dr. Manan Mewada (works at: Intel Corporation / Sankalp Semiconductors): PhD defense completed in February 2020
    • Dr. Ankur Changela (faculty at Indus University): PhD defense completed in October 2021
  • Ongoing:
    • Yagnik Bhavsar: (Status: 1st year course work, and initial research work on Computer vision for Road Safety)
    • Anurag Lakhlani: (Status: Completed PhD Comprehensive, and working on Research proposal)
  • Looking forward to guiding new PhD students...

Mazad S. Zaveri has taught courses in the digital VLSI/Electronics area, such as: Digital CMOS VLSI Design, VLSI Sub-system Design, Computer Organization, Embedded Systems using ATMEGA microcontrollers, Digital Logic Design and Verilog HDL, Basic Electronic Circuits.

Journal Papers

1. Mazad Zaveri and D. Hammerstrom, “CMOL/CMOS implementations of Bayesian polytree inference: Digital & mixed-signal architectures and performance/price,” IEEE Transactions on Nanotechnology, vol. 9(2), pp. 194-211, Mar. 2010. DOI: https://doi.org/10.1109/TNANO.2009.2028342 (IEEE Xplore, SCOPUS, WoS)
2. Mazad Zaveri and D. Hammerstrom, “Performance/Price Estimates for Cortex-Scale Hardware: A Design Space Exploration,” Neural Networks (Official Archival Journal of the International Neural Network Society, the European Neural Network Society, and the Japanese Neural Network Society), vol. 24(3), April 2011, Elsevier, pp.291-304. DOI: https://doi.org/10.1016/J.NEUNET.2010.12.003 (SCOPUS, WoS)
3. Pavan Vyas and Mazad Zaveri. "Verilog implementation of a node of hierarchical temporal memory," Asian Journal of Computer Science and Information Technology, vol. 3(7), pp. 103-108, July 2013. (ISSN: 2249-5126)
4. Nilay Mehta, Mazad Zaveri, "Investigation of Communication Schemes for ANN Implementation - Multiple Processing nodes (Based on FPGA/u-controller Boards)," Journal of Maharaja Sayajirao University of Baroda (Science and Technology), Feb. 2017. (ISSN: 0025-0422)
5. Manan Mewada, Mazad Zaveri, Rajesh Thakker, “Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures”, Integration, vol. 69, November 2019, Elsevier, pp. 381-392. DOI: https://doi.org/10.1016/j.vlsi.2019.09.002 (SCOPUS, WoS)
6. Ankur Changela, Mazad Zaveri, Deepak Verma, “FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm”, Integration, vol. 73, July 2020, Elsevier, pp. 89-100. DOI: https://doi.org/10.1016/j.vlsi.2020.03.008 (SCOPUS, WoS)
7. Manan Mewada, Mazad Zaveri, Ratnik Gandhi, Rajesh Thakker, “Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model”, Procedia Computer Science, vol. 171, June 2020, Elsevier, pp. 999-1008. DOI: https://doi.org/10.1016/j.procs.2020.04.107 (SCOPUS)
8. Ankur Changela, Mazad Zaveri, Deepak Verma, “Mixed-Radix, Virtually Scaling-Free CORDIC Algorithm Based Rotator for DSP Applications”, Integration, Elsevier, May 2021. (SCOPUS) DOI: https://doi.org/10.1016/j.vlsi.2021.01.005

Book Section/Chapter

1. C.-H. Luk, M. S. Zaveri, D. Hammerstrom, and R. J. Kerr, “Vision-Based Hazard Detection,” in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering System Design, vol. 16, C. H. Dagli, A. L. Buczak, D. L. Enke, M. Embrechts, and O. Ersoy, Eds. ASME Press:NY, 2007, pp. 439-444. DOI: https://doi.org/10.1115/1.802566 (AMSE)
2. M. S. Zaveri and D. Hammerstrom, “Chapter 4. CMOL/CMOS Implementations of Bayesian Inference Engine: Digital & Mixed-signal Architectures and Performance/price – A Hardware Design Space Exploration” in CMOS Processors and Memories, Kris Iniewski Ed., Aug. 2010, Springer, pp. 97-138. DOI: https://doi.org/10.1007/978-90-481-9216-8_4 (WoS)
3. Manan Mewada, Mazad Zaveri, Anurag Lakhlani, “Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions,” in VLSI Design and Test, Book series: Communications in Computer and Information Science, Kaushik B., Dasgupta S., Singh V. (Eds.), vol. 711, Dec. 2017, Springer, pp 15-23. DOI: https://doi.org/10.1007/978-981-10-7470-7_2 (WoS)

Conference Papers/Presentations (and posters)

1. C.-H. Luk, M. S. Zaveri, D. Hammerstrom, and R. J. Kerr, “Vision-Based Hazard Detection,”  in Conf. on Artificial Neural Networks in Engineering (ANNIE), St. Loius-MI, Nov. 2007.
2. C. Gao, M. S. Zaveri, and D. Hammerstrom, “CMOS / CMOL architectures for spiking cortical column,” in IEEE World Congress on Computational Intelligence – Int. Joint Conf. on Neural Networks (WCCI-IJCNN), Hong Kong, June 2008, pp. 2442-2449. DOI: https://doi.org/10.1109/IJCNN.2008.4634138 (IEEE Xplore, SCOPUS, WoS)
3. D. Hammerstrom and M. S. Zaveri, “Bayesian memory, a possible hardware building block for intelligent systems,” in AAAI Fall Symposium Series on Biologically Inspired Cognitive Architectures , Arlington, VA, TR FS-08-04, Nov. 2008, AAAI Press, pp. 81. URL: https://www.aaai.org/Papers/Symposia/Fall/2008/FS-08-04/FS08-04-021.pdf  (SCOPUS)
4. M. S. Zaveri and D. Hammerstrom, “Prospects for Building Cortex-Scale CMOL/CMOS Circuits: A Design Space Exploration,” in IEEE Norchip Conference, Trondheim-Norway, Nov. 2009. DOI: https://doi.org/10.1109/norchp.2009.5397858 (IEEE Xplore, SCOPUS)
5. M. S. Zaveri, D. Voils, and D. Hammerstrom, “Using computational neuroscience to build better computers,” (poster) in The Science and Business of the Brain: Oregon Innovation Showcase, I-C-Oregon, Portland-OR, Nov. 2009.
6. N.B. Ambasana and M. S. Zaveri, "Analysis of increased parallelism in FPGA implementation of neural networks for environment/noise classification and removal," in Nirma University International Conference on Engineering, Ahmedabad, Dec. 2012, pp.1-5. DOI: https://doi.org/10.1109/NUICONE.2012.6493242 (IEEE Xplore, SCOPUS)
7. Chhaya, Vaibhav and Zaveri, Mazad S."CMOS Current-based Mixed-Signal Architecture for Vector-Matrix Multiplication", in National Conference on Recent Advances in Communication, Control and Computing Technology, Surat, March, 2012, pp. 137-143. (Benison Education, ISBN: 978-81-88894-34-5)
8. Shalini Rankawat, Mansi Rankawat, Rahul Dubey, Mazad Zaveri,"Robust Heart Rate Estimation From Multiple Cardiovascular and Non-cardiovascular Physiological Signals Using Signal Quality Indices and Kalman Filter", in International Conference on Communications and Quantum Systems, Singapore, Jan. 2015. URL: https://publications.waset.org/abstracts/17506/pdf
9. Tejas Dalal, Mazad Zaveri, "Hardware Implementation of MLP and RBF Neural Networks onto Multiple Processing Nodes", in International Conference on Multidisciplinary Research & Practice, paper ID 220, AMA Ahmedabad, November 2014. Proceedings appeared in International Journal of Research and Scientific Innovation, vol. 1(7), Nov. 2014, pp. 132-137. (ISSN: 2321-2705)
10. Manan Mewada, Mazad Zaveri, "An Improved Input Test Pattern for Characterization of Full Adder Circuits”, in International Conference on Multidisciplinary Research & Practice, paper ID 152, AMA Ahmedabad, December 2015. Proceedings appeared in International Journal of Research and Scientific Innovation, vol. 3(1), Dec. 2015, pp. 222-226. (ISSN: 2321 – 2705)
11. Manan Mewada, Mazad Zaveri, “A Low-Power High-Speed Hybrid Full Adder", in International Symposium on VLSI Design and Test (VDAT), IIT Guwahati-Assam, 24 - 27 May 2016. DOI: https://doi.org/10.1109/ISVDAT.2016.8064900  (IEEE Xplore, SCOPUS, WoS)
12. Manan Mewada, Mazad Zaveri, “An Input Test Pattern for Characterization of a Full-Adder and n-bit Ripple Carry Adder”, in International Conference on Advances in Computing, Communications and Informatics, September 2016, LNMIIT-Jaipur, September 2016. DOI: https://doi.org/10.1109/ICACCI.2016.7732055 (IEEE Xplore, SCOPUS, WoS)
13. Nilay Mehta, Mazad Zaveri, "Investigation of Communication Schemes for ANN Implementation - Multiple Processing nodes (Based on FPGA/u-controller Boards)" in (ISTE, UGC merged scheme funded) International Conference on Advances in Computing, Communication, and Informatics, held on 25-Feb-2017, at the Dept. of CSE, Maharaja Sayajirao University, pp. 20-26. Proceedings appeared in MSU journal. (Best paper award in Session 1-2)
14. Manan Mewada, Mazad Zaveri, Anurag Lakhlani, “Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder using Reduced Input Transitions,” in International Symposium on VLSI Design and Test (VDAT), IIT-Roorkee, June-July 2017. DOI: https://doi.org/10.1007/978-981-10-7470-7_2 Proceedings appeared as book chapter. (WoS)
15. Ankur Changela, Mazad Zaveri, Anurag Lakhlani, “FPGA Implementation of Asynchronous Mousetrap Pipelined Radix-2 CORDIC Algorithm,” in IEEE International Conference on Current trends towards Converging Technologies, Coimbatore - India, 1 - 3 March 2018, PID 7092. DOI: https://doi.org/10.1109/ICCTCT.2018.8551112 (IEEE Xplore, SCOPUS)
16. Ankur Changela, Mazad Zaveri, Anurag Lakhlani, “ASIC Implementation of High Performance Radix-8 CORDIC Algorithm,” (IEEE sponsored) International Conference on Advances in Computing, Communications and Informatics, Bangalore - India, 19 – 22 September, 2018. DOI: https://doi.org/10.1109/ICACCI.2018.8554883 (IEEE Xplore, SCOPUS, WoS)
17. Manan Mewada, Mazad Zaveri, Ratnik Gandhi, Rajesh Thakker, “Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model”, in Third International Conference on Computing and Network Communications (CoCoNet'19), IIITM-K Trivandrum, Kerala,, December 18-21, 2019. (Proceedings appeared in journal)  (SCOPUS)
18.  Mehul Raval, Tolga Kaya, Mazad Zaveri, Paawan Sharma, "Experiments with Multinational Cross-Course Projects through Blended Learning", IEEE TALE2020 – An International Conference on Engineering, Technology and Education, Dec. 2020. pp.65-70. DOI: https://doi.org/10.31219/osf.io/ph3e5 (pre-print)        https://doi.org/10.1109/TALE48869.2020.9368362 (IEEE Xplore)

Dissertation as Book

1. M. S. Zaveri, "CMOL/CMOS hardware architecture and performance/price for Bayesian memory - The building block of intelligent systems," PhD dissertation, Dept. of Electrical and Computer Engineering, Portland State University, Nov. 2009. (ProQuest-UMI: Pub No.: 3391676) (http://www.worldcat.org/oclc/550656475)