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A hardware acceleration/simulation platform based on multiple boards


Building a (programmable) hardware acceleration/simulation platform based on multiple boards (FPGA or Arduino boards), for emulating neural networks/algorithms. (Initial case study: Palm Associative Memory)

Description

This project will attempt to create an indigenous expandable multi-board (FPGA or Arduino boards) acceleration/simulation platform for (implementing/emulating) neural network/algorithm. The project would involve the development of the algorithm-specific computational architecture (coded in Verilog HDL) within each board (also referred to as the Processing Node in the figure below), and algorithm-specific inter-board communication scheme (coded in Verilog HDL). The computational architecture (and the communication scheme) would be programmable, in terms of: the number of neurons & synapses, function of neuron, and possibly in terms of neural connectivity/topology. Improvements in performance, due to possible distribution of the sub-operations of the algorithm over the FPGA or Arduino boards, and parallelization within each FPGA board (not possible in Arduino board), could be explored.

Related outcomes/deliverables would be: Code repository (implementations of) various neural networks, such as: MLP NN, RBF NN, Hopfield, BAM, etc., onto multiple boards (FPGA or Arduino boards), that can be used by SEAS students for other courses, such as: Machine Learning, etc.

 

Faculty

Other Members

  • Pal Nikola
  • Dev Mehta