In December 2014, Mazad S. Zaveri joined the Institute of Engineering and Technology (now known as SEAS) - Ahmedabad University (AU), as assistant professor. During 2010-2014, he worked as assistant professor, at the Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar. During Jan-May 2014, he was also a visiting faculty at the Indian Institute of Information Technology, Vadodara. During 2003-2009, he worked as research assistant at the (erstwhile "Oregon Graduate Institute") Oregon Health and Science University, and Portland State University.
Mazad S. Zaveri got his PhD in Electrical and Computer Engineering from Portland State University in 2009, his MSE in Electrical Engineering from Arizona State University in 2003, and his BE in Instrumentaton and Control Engineering from Gujarat University in 2000. He passed his HSC and SSC (school certification exams) from St. Xavier's School - Loyola Hall, Ahmedabad.
Mazad S. Zaveri's research interests are in the digital "neuro-morphic VLSI" area, which means digital VLSI circuits/architectures/platforms that emulate neural networks (or other more abstract cortical models). He has guided several MTech and BTech Theses/Projects, mostly related to the digital neuro-morphic VLSI area.
Mazad S. Zaveri has taught courses related to the VLSI/Electronics area, such as: Introduction to VLSI design, VLSI Sub-systems, Digital Logic Design, and Basic Electronic Circuits.
Mazad S. Zaveri is a Parsi-Zoroastrian, whose native place is Devgadh Baria (in Panchmahal/Dahod district of Gujarat).
Visit my website: https://sites.google.com/site/mazadzaveri/
- Digital CMOS VLSI Circuits and Architectures for Neural Networks
- Low power-delay product arithmetic/logic CMOS circuits (or VLSI sub-systems)
- Low power-delay product asynchronous CMOS circuits for CORDIC
- Manan Mewada, Mazad Zaveri, "An Improved Input Test Pattern for Characterization of Full Adder Circuits”, in International Conference on Multidisciplinary Research & Practice, AMA-Ahmedabad, 24th December 2015, pp. 222-226.
- Manan Mewada, Mazad Zaveri, “A Low-Power High-Speed Hybrid Full Adder," in (IEEE sponsored) International Symposium on VLSI Design and Test (VDAT), IIT-Guwahati, 24th-27th May 2016.
- Manan Mewada, Mazad Zaveri, “An Input Test Pattern for Characterization of a Full-Adder and n-bit Ripple Carry Adder,” in (IEEE sponsored) International Conference on Advances in Computing, Communications and Informatics, 21st-24th September 2016, LNMIIT-Jaipur, September 2016.
- Nilay Mehta, Mazad Zaveru, "Investigation of Communication Schemes for ANN Implementation - Multiple Processing nodes (Based on FPGA/u-controller Boards)" in UGC merged scheme funded International Conference on Advances in Computing, Communication, and Informatics, 25-Feb-2017, Department of Computer Science and Engineering, Maharaja Sayajirao University of Baroda. (Best paper award in Session 1 / Session 2)
Teaching at SEAS
- Digital Design (BTech ICT Semester-2)
- VLSI Sub-system Design (BTech ICT Semester-6)
- VLSI Design (BTech ICT Semester-5)
- Circuit Characterization for VLSI Sub-systems (BTech ICT Semester-7)
- Chair, PhD Program, SEAS
- Member, School Level Academic Program Committee, SEAS
- Member, School Level Doctoral Program Committee, SEAS
- Member, School Level Examination Committee, SEAS
236, School of Engineering and Applied Science,
Ahmedabad Education Society FP. 4,
Near Commerce Six Roads,
Navrangpura, Ahmedabad - 380 009, India