Faculty

Professor Shrimali completed his Bachelor of Engineering from Nirma Institute of Technology, Master of Technology from Indian Institute of Technology, Kharagpur, and PhD from Indian Institute of Technology Delhi.

Previously, he served as a faculty at IIT Mandi's School of Computing and Electrical Engineering and STMicroelectronics (Greater Noida) as a senior design engineer. He also worked with Università degli Studi di Milano as a post-doctorate researcher and was associated with Istituto Nazionale di Fisica Nucleare (INFN), Milano.

Professor Shrimali received the Young Faculty Research Fellowship of Ministry of Electronics and Information Technology (MEITy), Government of India, the Young Faculty Fellowship of IIT Mandi, and the Distinguished Alumni Award of Nirma University.

Design and Testing of Radiation Hard Circuits [CMOS silicon detectors and dosimeter], Analog and Mixed Signal VLSI Design (ADCs and Atomic Clock), Signal and Power Integrity (SI/PI), On-chip Instrumentation, and Modelling of Radiation Effects on Analog and Mixed Signal Circuits

Granted Patents

• Kunwar, U., Chaturvedi, P., and Shrimali, H. (2024). Fully automated electrostatic page turning technique and device for document scanning. Indian patent application number 201911044970.
• Dhiman, S., Gupta, N., and Shrimali, H. (2024). Method of running an unrolled binary search or multiple level search for pipeline ADC. Application number: 202013054196.

Filed Patents

• Sakre, M., Sheikh, R. Z., Nagulapalli, R., and Shrimali, H. (2020). A voltage-controlled oscillator (LC VCO) and method of operation thereof. Application number: 202411032951.
• Dinesh, B., Gupta, N., and Shrimali, H. (2020). Adaptive hybrid analog-to-digital converter with fractional/multi bit per cycle conversion. Indian patent, application number 202013054196.
• Dinesh, B., Gupta, N. and Shrimali, H. (2020). Hybrid analog-to-digital converter with fractional/multi bit per cycle conversion. Indian patent, application number 202011053662.
• Joshi, A., Shrimali, H., and Sharma, K. S. (2019). "Reconfigurable Reduced Switching Activity (RSW) Mode for an Analog-To-Digital Converter. Indian patent, application number 201911042977.

Peer Reviewed International Journals

• Dhimaan, S., and Shrimali, H. (2024). On Minimizing Charge Injection Error Using Multi-Dummy Switches with Enhanced Linearity. Elsevier VLSI Integration, vol. 97, pp. 102175. (DOI: 10.1016/j.vlsi.2024.102175).
• Sharma, V. K., Tripathi, J. N., and Shrimali, H. (2022). Indefinite Admittance Matrix based Modelling of PSIJ in Nano-Scale CMOS I/O Drivers. IEEE Open Access Journal of Nanotechnology, Early Access, pp. 1 – 10.
• Illikkal, S., Tripathy, N. J., Sharma, K. V., Shrimali, H., Achar, R. (2022). Novel Observations and Physical Insight on PSIJ Behaviour in CMOS Chain-of-inverters. in IEEE Access, pp. 100172 – 100177, Sept. 2022.
• Sharma, S., Khosla, R., Das, S., and Shrimali, H., and Sharma, K. S. (2022). Two-dimensional Van Der Waals Hafnium Disulfide and Zirconium Oxide-based Micro-Integrated Electrodes Transistors. IEEE TED, Early Access, 1-7.
• Sharma, K. V., Tripathi, N. J., Shrimali, H. (2022). Design and Distortion Analysis of a Power Delivery Network in the Presence of Internal Supply Noise. IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), Vol. 12, Issue 7, pp. 1130 – 1139.
• Balasubramanian, D. and Shrimali, H. (2022). Design and Implementation of a Second Order PLL based Frequency Synthesizer for Implantable Medical Devices. Elsevier: Integration the VLSI Journal, Vol. 86, Pg. 57-63.
• Pandey, S. K., and Shrimali, H. (2022). Novel VLSI Architectures and Micro-cell Libraries for Subscalar Computations. IEEE Access, vol. 10, pp. 56985-56995.
• Sharma, V. K., Tripathi, J. N., and Shrimali, H. (2021). Analysis of Power Supply Noise in AMS Circuits including the effects of Interconnects using Estimation. Elsevier AEUE – International Journal of Electronics and Communications, Vol. 139, pp. 153913.
• Arora, P., Tripathi, J. N., and Shrimali, H. (2021). A Device Parameters based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters. Transactions on Electron Devices (TED), pp. 3268-3275, Vol. 68, Issue 7.
• Gupta, N., Makosiej, A., Shrimali, H., Amara, A., Vladimirescu, A., and Anghel, C. (2021). Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C DRAM. IEEE Transactions on Nanotechnology, Vol. 20, pp. 270-227.
• Joshi, A., Shrimali, H., and Sharma, S. K. (2021). Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC. Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Vol. 68, Issue 7, pp. 2317-2321.
• Joshi, A., Shrimali, H., and Sharma, S. K. (2020). A Discrete-Time MOS Parametric Amplifier based Chopped Signal Demodulator. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 28, No. 11, pp. 2268-2279.
• Sharma, V. K., Tripathi, J. N., and Shrimali, H. (2020). Deterministic Noise Analysis in Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix. IEEE Open Journal of Circuits and Systems (OJCAS), Vol. 1, pp. 124-139.
• Joshi, A., Shrimali, H., and Sharma, S. K. (2020).  Reduced Switching Mode for a SAR ADC: Analysis and Design of a SAR A-to-D Algorithm with Periodic Stand-by Mode Circuit Components. IET Circuits, Devices & Systems, Vol. 14, Issue 5, pp. 686-694.
• Dinesh, B., Pandey, S. K., Gupta, N., and Shrimali, H. (2020). Design of hybrid flash-SAR ADC using an inverter-based comparator in 28 nm CMOS. Elsevier Microelectronics, Vol. 95, 104666.
• Tripathi, J. N., Illikkal, S., Shrimali, H., & Achar, R. (2019). A Thomas Algorithm based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers. IEEE Access, Vol. 7, pp. 125240-125252.
• Yadav, I., and Shrimali, H. (2019). Noise and Crosstalk Models of the Particle Detector with Zero-Pole Transformation Charge Sensitive Amplifier. Elsevier Nuclear Instruments and Methods in Physics Research: A, Vol. 937, pp. 107-116.
• Sharma, S., Das, S., Khosla, R., Shrimali, H., & Sharma, S. K. (2019). Realization and Performance Analysis of Facile Processed µ-IDE based multi-layer HfS2/HfO2 Transistors. IEEE Transaction on Electron Devices, vol. 66, no. 7, pp. 3236-3241.
• Sharma, S., Das, S., Khosla, R., Shrimali, H., & Sharma, S. K. (2019). Highly UV sensitive Sn Nanoparticles blended with polyaniline onto Micro-Interdigitated Electrode Array for UV-C detection applications. Journal of Materials Science: Materials in Electronics, Vol. 30, Issue 8, pp 7534-7542.
• Tripathi, J. N., Arora, P., Shrimali, H., and Achar, R. (2018). Efficient Jitter Analysis for a Chain of CMOS Inverters. IEEE Transactions on Electromagnetic Compatibility, Vol. 10, pp. 1-11.
• Tripathi, J. N., Sharma, V., and Shrimali, H. (2018). A Review on Power Supply Induced Jitter. IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), Vol. 9, Issue 3, pp. 511 - 524.
• Sharma, S., Das, S., Shrimali, H., & Sharma, S. K. (2018). High-Performance CSA-PANI based Organic Phototransistor by Elastomer Gratings. Elsevier Journal of Organic Electronics, Vol. 57, pp. 14-20, pp. 14-20.
• Yadav, I., Shrimali, H., Andreazza, A., and Liberali, V. (2018). Analytical Expressions for Noise and Crosstalk Voltages of the High Energy Silicon Particle Detector. Journal of Instrumentation, Institute of Physics (IOP) science, Vol. 13, pg. C01019.
• Sharma, S., Khosla, R., Deva, D., Shrimali, H., & Sharma, S. K. (2017). Fluorine-chlorine co-doped TiO2/CSA doped polyaniline based high performance inorganic/organic hybrid heterostructure for UV photodetection applications. Elsevier Sensors & Actuators: A. physical, Vol. 261, pp. 94-102.
• Joshi, A., Shrimali, H., and Sharma, S. K. (2017). A Systematic Design Approach for a Gain Boosted Telescopic OTA with Cross Coupled Capacitor. IET Circuits, Devices & Systems, Vol. 11, Issue 3, pp. 225 - 231.
• Andreazza, A., Castoldi, A., Ceriale, V., Chiodini, G., Citterio, M., Darbo, G., Gariano, G., Gaudiello, A., Guazzoni, C., Joshi, A., Liberali, V., Passadore, S., Ragusa, F., Ruscino, E., Sbarra, C., Sidoti, A., Shrimali, H., Stabile, A., Yadav, I., and Zaffaroni, E. (2016). HV-CMOS detectors in BCD8 technology. Journal of Instrumentation, Institute of Physics (IOP) science, Vol. 11, pp. C11038.
• Shrimali, H., and Chatterjee, S. (2015). A Technique to Linearize the Discrete-Time Parametric Amplifier and its Variants. Elsevier Microelectronics Journal, Vol. 46, No. 11, pp. 1033-1038.
• Shrimali, H., and Liberali, V. (2014). Parametric Amplifier based Dynamic clocked Comparator. Elsevier Solid State Electronics, Vol. 101, pp. 85-89.
• Camplani, A., Shojaii, S., Shrimali, H., & Liberali, V. (2014). CMOS IC Radiation Hardening by Design. FACTA Universitatis, Journal series: Electronics and Energetics Vol. 27, No. 2, pp.251–258.
• Shrimali, H., & Chatterjee, S. (2011). Distortion analysis of a three terminal MOS-based discrete time parametric amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 12, pp. 902-905.

Peer Reviewed International Conferences

• Yaseen NJ, A., Shrimali, H., and Das, D. (2024, June). A 66-dBΩ 5-GHz and 44.88-√Hz/(pA·pW) Inductorless Transimpedance Amplifier in 65-nm CMOS. IEEE MIXDES.
• Dhimaan, S., and Shrimali, H. (2024, May). A 12.7 Bit Accurate and 5.3 nJ·μV2·ns Comparator with Dynamic-cum-Body Bias Technique in SOI. IEEE ISCAS, Singapore, May 2024.
• Sowmyasree, S., and Shrimali, H. (2024, January). An On-chip Thermoelectric Cooler Controller with Improved Driving Current of 2A at 0.5 Ω Load. IEEE VLSI Design Conference, Kolkata, India.
• Sowmyasree, S., and Shrimali, H. (2023, December). Fully Monolithic 1A Thermoelectric Cooler Controller with 90% Efficiency" in IEEE ICECS, Istanbul, Turkey.
• Sowmyasree, S., and Shrimali, H. (2023, January). A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 µV rms noise and 80 dB of PSRR. IEEE VLSI Design Conference, Hyderabad, India.
• Gowtham, P., Goel, R., and Shrimali, H. (2021, December). Design of CMOS Device Process Sensor in 28 nm FD-SOI with 2% of Frequency Spread. IEEE International Conference on Electronics Circuits and Systems (ICECS), UAE.
• Gupta, N., Shrimali, H., Makosiej, A., Vladimirescu, A., and Amara, A. (2021, August). Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).
• Arora, P., Tripathi, J. N., and Shrimali, H. (2021, June). Analytical Modeling of Jitter in CMOS Inverters Due to Periodic Fluctuations in Power Supply", in IEEE NEWCAS, pp. 1-4.
• Dinesh, B., Shrimali, H., and Nallam, N. (2021, May). A Low-Power Quadrature LC− Oscillator Using Core-and-Coupling Current-Reuse. IEEE ISCAS, pp. 1-5.
• Sharma, V. K., Tripathi, J. N., and Shrimali, H. (2020, October). An Inspection Based Method to Analyse Deterministic Noise in N-port Circuits. IEEE EPEPS 2020, pp-1-3.
• Sharma, V. K., Tripathi, J. N., and Shrimali, H. (2020, May). A Generalized Approach for Analyzing the Impact of Supply Noise in MOS Amplifiers. IEEE SPI 2020, pp- 1-4.
• Dhiman, S., Sharma, V. K., and Shrimali, H. (2020, October). Design and Analysis of Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application. IEEE ISCAS, Seville, Spain.
• Yadav, I., Joshi, A., Ruscino, E., Liberali, V., Andreazza, A., and Shrimali, H. (2019, November). Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements. IEEE ICECS, Genova, Italy.
• Dhiman, S., Yadav, I., and Shrimali, H. (2019, November). Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology. Asia Pacific Conference on Circuits and Systems (APCCAS), Bangkok, Thailand.
• Pandey, K. S., Dinesh, B., Goel, N., and Shrimali, H. (2019, June). An Ultra-Fast Parallel Prefix Adder. IEEE Computer Arithmetic (Arith), Kyoto, Japan.
• Illikkal, S., Tripathi, J., and Shrimali, H. (2019, June). Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network. IEEE APEMC, Sapporo, Japan.
• Sharma, V. K., Dinesh, B., Illikkal, S., Tripathi, J. N., Gupta, N., and Shrimali, H. (2019, May). Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator. IEEE ISCAS, Sapporo, Japan, May. 2019.
• Dinesh, B., Gupta, N., and Shrimali, H. (2019, May). A 6-Bit 29.56 fJ/conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS. IEEE ISCAS, Sapporo, Japan.
• Illikkal, S., Tripathi, J., and Shrimali, H. (2019, March). Analyzing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter. IEEE International Conference on Signal Processing and Integrated Networks, SPIN, Delhi.
• Tripathi, I., Joshi, A., Ruscino, E., Andreazza, A., Liberali, V., and Shrimali, H. (2019, January). Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process. International Conference on VLSI Design (VLSID), Delhi, India.
• Sharma, V., Tripathi, J., and Shrimali, H. (2018, December). Extension of EMPSIJ Method for Substrate Noise Induced Jitter: an Inverter Case Study. IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Chandigarh, India.
• Sharma, V., Tripathi, J., and Shrimali, H. (2018, December). A Quick Assessment of Nonlinearity in Power Delivery Networks. IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Chandigarh, India.
• Deo, A., Pandey, S. K., Joshi, A., Sharma, S. K., and Shrimali, H. (2018, June). Design of a Third Order Butterworth Gm-C Filter for EEG Signal Detection Application. IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland.
• Joshi, A., Shrimali, H., and Sharma, S. K. (2018, May). The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, pp-1-5.
• Shrimali, H., Sharma, V., Tripathi, J., and Malik, R. (2017, December). Nonlinear Modeling and Analysis of Buck Converter using Volterra Series. IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, pp-222-226.
• Sharma, V., Tripathi, J., Shrimali, H., and Malik, R. (2017, December). The Harmonics Impact Study of a DC-DC Buck Converter through a Power Delivery Network. IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Hangzhou, China, pp-1-3.
• Kumar, D. B., and Shrimali, H. (2017, November). Design of a 520 μW, –141 dBc/Hz and 450 MHz Frequency Synthesizer Using Low Power and Low Phase Noise Current Reuse VCO. IEEE TENCON, Penang, Malaysia, pp-2937-2912.
• Sharma, V., Shrimali, H., Tripathi, J., and Malik, R. (2017, November). Distortion Analysis for a DC-DC Buck Converter. International SoC design conference (ISOCC), Seoul, Korea, pp-212-213 (Got the ISOCC Best Paper Award).
• Andreazza, A., Castoldi, A., Ceriale, V., Chiodini, G., Citterio, M., Darbo, G., ... and Zaffaroni, E. (2016, October-November). HV-CMOS detectors for High Energy Physics: characterization of BCD8 technology and controlled hybridization technique. IEEE Nuclear Science Symposium 2016 (NSS), pp. 1-3.
• Joshi, A., Yadav, I., Sharma, S., and Shrimali, H. (2016, October). The Pole-zero Doublet: a Cascode Operational Amplifier with Cross Coupled Capacitor. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi (UAE), pp. 1-4.
• Tripathi, J., Sharma, V., Advani, H., Singh, P., Shrimali, H., and Malik, R. (2016, May). An Analysis of Power Supply Induced Jitter for a Voltage Mode Driver in High-speed Serial Links. IEEE Workshop on Signal and Power Integrity (SPI), Turin, Italy, pp-1-4.
• Shrimali, H., and Liberali, V. (2014, December). The Start-up Circuit for a Low Voltage Bandgap Reference. IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, pp. 92-95.
• Shrimali, H., and Liberali, V. (2014, June). A Threshold Voltage Modeling for A Spacer-Trapping Memory Cell Using Verilog-A. Workshop on Compact Modeling (WCM), Washington, USA, pp. 529-532.
• Shrimali, H. (2013, December). Discrete Time Parametric Amplifier based Dynamic clocked Comparator. International Semiconductor Device Research Symposium (ISDRS) 2013, Bethesda (Maryland).
• Shrimali, H., and Chatterjee, S. (2011, May). Third Order Harmonic Cancellation Technique for a Parametric Amplifier. IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 1880–1883.
• Shrimali, H., and Chatterjee, S. (2011, May). 11 GHz UGBW Op-amp with feed-forward compensation technique. IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 17–20.

• CMOS Analog IC design 
• Digital MOS LSI Circuits 
• CMOS Digital IC Design Practicum
• EE619 – Mixed Signal VLSI Design 
• Analog Circuit Design 
• [February-June 2019 and August-December 2019]: EE203 – Network Theory (BTech EE – Core Course)
• [February-June 2015, 2016, and 2017]: IC161 – Applied Electronics (BTech – Institute Core Course)
• [February-June 2015, 2016, and 2017]: IC161P – Applied Electronics laboratory (BTech – Institute Core Course)
• [August-December 2021] IC101P – Reverse Engineering (Co-coordinator) (BTech – Institute Core Course)
• [February-June 2021, 2022] IC201P – Design Practicum (Co-coordinator) (BTech – Institute Core Course)
• [August-December 2015, 2016, 2017, 2022]: DP504P – Electrical and Mechanical Workshop (for MSc students) (MSc – Core Course)